This book chapter describes, explores, and analyzes the designs and framework for energy-efficient and reliable edge computing from device to architecture to handle and compute data-intensive tasks and applications. First, we present a comprehensive study regarding magnetic random-access memory (MRAM) as a promising nonvolatile memory component due to its interesting features, including nonvolatility, near-zero standby power, high integration density, and radiation hardness. To enable efficient and reliable computing units, optimized in-memory processing accelerators for data and compute-intensive tasks via algorithm and hardware codesign approaches are discussed. Moreover, two other high attention topics, namely, normally off computing and hardware security, are examined. Thus, two design methodologies are introduced to mitigate MRAM write energy cost while provided benefits are efficiently utilized. The first design methodology approach, referred to as NV-clustering, is developed to realize middleware-transparent intermittent computing. The foundations of our work are advanced from the ground up by extending this emerging MRAM device to discover logic-in-memory methods that leverage intrinsic nonvolatility to realize intermittent robust computation. Then power analysis-resilient circuit (PARC) procedure as an extension of NV-clustering is developed as a power-masked synthesis technique in the presence of power analysis attacks.

Abstract

Aggressive Metal Oxide Semiconductor (MOS) technology scaling in digital circuits has resulted in important challenges including a significant increase in leakage currents, shortchannel effects, and drain saturation growth while reducing the power supply voltage for digital
applications. Furthermore, by extensions to sub 10-nm regimes, error resiliency has become a major challenge for the microelectronics industry, particularly mission-critical systems, e.g. space and terrestrial applications. Therefore, emerging devices and technologies have attracted considerable
attention in recent years as an alternative for CMOS based technologies such as spintronics [1-6], resistive random access memory (RRAM) [7-10], phase-change memory (PCM) [11, 12], and Quantum Cellular Automata (QCA) [13-18]. Among promising devices, the 2014 Magnetism
Roadmap [19] identifies nanomagnetic devices as capable post-CMOS candidates, of which Magnetic Tunnel Junctions (MTJs) are considered as one of the most promising technologies spanning both logic [20-22] and memory functionalities [23-26]. MTJs are characterized by nonvolatility, near-zero standby power, high integration density, and radiation-hardness, as a technology progression from CMOS. Moreover, MTJ can be readily integrated at the back-end process of the CMOS fabrication, due to its vertical structure [27, 28]. In this book chapter, we will focus on the fundamentals and modeling of the MTJs using precise physics equations. Moreover, some of their applications in reconfigurable fabrics and logic-in-memory architectures will be studied.

Abstract

In this paper we have proposed an efficient method based on Genetic Algorithms (GAs) to design quantum cellular automata (QCA) circuits with minimum possible number of gates. The basic gates used to design these circuits are 2-input and 3-input NAND gates in addition to inverter gate. Due to use of these two types of NAND gates and their contradictory effects, a new fitness function has been defined. In addition, in this method we have used a type of mutation operator that can significantly help the GA to avoid local optima. The results show that the proposed approach is very efficient in deriving NAND based QCA designs.